(a) Field of the Invention
The present disclosure is directed to electronic processing systems, and more particularly, to a multiprocessor system having a direct transfer function for program status information in a multilink architecture.
(b) Discussion of the Related Art
Recently developed mobile communication systems, such as, multimedia electronic instruments such as a portable multimedia player (PMP) or handheld phone (HHP), or a personal data assistant (PDA) etc., employ plural processors within one system to obtain increased speed and smoother operation. For example, in handheld phones, in addition to the basic telephone function, other functionality, such as music, games, camera, payment, moving pictures, etc. may be realized according to users' preferences. Such devices therefore need to employ both a communication processor with a communication modulation/demodulation function and an application processor with an application function, except that the communication function is incorporated in a printed circuit board (PCB) within the handheld phone.
In such multiprocessor system, a semiconductor memory such as a dynamic random-access memory (DRAM) etc. employed to store processing data may be altered in view of operation or function. For example, it may be required to simultaneously input/output data through a plurality of respective access ports by employing the plurality of access ports.
In general, a semiconductor memory device having two access ports is called a dual-port memory. A typical dual-port memory used as an image processing video memory has a random access memory (RAM) port accessible in a random sequence and a serial access memory (SAM) port accessible only in a serial sequence. On the other hand, a dynamic random access memory which does not employ an SAM port and for which a shared memory area of a memory cell array constructed of DRAM cells is accessible by respective processors through a plurality of access ports, is called herein a multiport semiconductor memory device or multipath accessible semiconductor memory device to be distinguished from the dual-port memory.
An exemplary multiprocessor system having a shared memory area accessible by a plurality of processors, disclosed in U.S. Publication No. 2003/0093628, by P. Matter et al. and published on May 15, 2003, is shown in FIG. 1.
Referring to FIG. 1 illustrating a block diagram of multiprocessor system 50, a memory array 35 is comprised of first, second and third portions. A first portion 33 of the memory array 35 is accessed only by a first processor 70 through a port 37, a second portion 31 is accessed only by a second processor 80 through a port 38, and a third portion 32 is accessed by both the first and second processors 70 and 80. Here, the size of the first and second portions 33 and 31 of the memory array 35 may vary depending upon an operation load of the first and second processors 70 and 80, and the memory array 35 may be implemented as either a memory type or disk storage type.
Realizing third portion 32 shared by the first and second processors 70 and 80 within memory array 35 in a DRAM involves addressing several issues. Exemplary issues include a layout of memory areas within the memory array 35 and an adequate read/write path control technique for respective ports.
An alternative multiprocessor system including a multimedia system may employ a structure such as that shown in FIG. 2.
FIG. 2 is a block diagram illustrating a memory connection structure of a typical multiprocessor system in a multimedia communication system. The system structure of FIG. 2 comprises two processors 10 and 20, one DRAM 30 and two flash memories 40 and 50.
In detail, a multiprocessor system adaptable to a mobile communication device such as a handheld phone comprises a multiport semiconductor memory device 30 (ONEDRAM®). First and second processors 10 and 20 employed in the multiprocessor system share the multiport DRAM 30. Thus the multiport semiconductor memory device 30 is individually coupled with the first and second processors 10 and 20 through system buses B1 and B2 and is accessed by all of the first and second processors 10 and 20. On the other hand, a first flash memory 40 is coupled to the first processor 10 through a system bus B4, and a second flash memory 50 is coupled to the second processor 20 through a system bus B3, thus each flash memory is accessed dedicatedly by each corresponding processor.
The structure of a multiprocessor system such as that shown in FIG. 2 does not allow a shared use of flash memory, and realizing such a system leads to increased costs and increased parts occupation area. Accordingly, a multilink architecture (MLA) package as shown in FIG. 3 is disclosed.
However, in the system of FIG. 3, a processor with an indirect connection may not recognize a program completion state of the flash memory.